A question regarding to MSIX interrupts for NVME

[Xuehua Chen]

> The spec also says: "It is recommended that interrupts for commands that
> complete in error are not coalesced."  So your design needs a way to
> defeat the coalescing and send the interrupt if an error completion is
> sent to a completion queue.  You can use the same mechanism to defeat
> the coalescing if any completion is sent to the admin completion queue.

This clarified some of my thoughts. What I said about it is strange
for hw to support interrupt
coalescing for IOCQ and ACQ sharing is not correct. And we can enable
interrupt coalescing
even when ACQ and IOCQ are shared. Thanks a lot for this!

The info seems to say that error handling better be handled asap. Then
it is more likely that the
same may apply to admin cq. The question I have is what are the
differences in response time
comparing allocating a separate vector for ACQ and sharing the
interrupt vector with IOCQ1.
When there are intensive IOs on IOQ1, if allocating a separate vector
that can be triggered on
a different cpu, the response time could be faster. Right now I don't
see disabling coalescing for
admin cq coalescing has much effect since it could be processed after
many IOCQ entries are
processed. In the mean time, other than an extra interrupt vector, do
you see any other disadvantages
if we allocate a separate vector for ACQ?

Thanks a lot!